module led_twinkle(
    input           clk,
    input           rst_n,
    output [1:0]    led
    );

reg [25:0] cnt;

assign led = (cnt < 26'd2500_0000-1) ? 2'b01 : 2'b10;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        cnt <= 26'd0;
    end else if(cnt < 26'd5000_0000-1) begin
        cnt <= cnt + 1'b1;
    end else begin
        cnt <= 26'd0;
    end
    
end


    
endmodule
